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fn7102 rev 7.00 page 1 of 14 may 8, 2006 fn7102 rev 7.00 may 8, 2006 el7566 monolithic 6a dc/dc step-down regulator datasheet the el7566 is a full-feature sy nchronous step-down regulator capable of up to 6a and 96% efficiency. the device operates from 3v to 6v input supply (v in ). with internal cmos power fets, the device can operate a t up to 100% duty ratio, allowing for an output voltage range of 0.8v to nearly v in . an adjustable switching frequency up to 1mhz enables the use of small components, thereby reducing board area consumption to under 0.72sq-in on one side of a pcb. the el7566 operates in constant frequency pwm mode, making external synchronization possible. a soft- start feature is integrated in the el7566 to limit in-rush currents and allow for a smooth voltage ramp from zero to regulat ion. other start-up features are integrated to add flexib ility for synchronizing many supplies in multiple configurations. the el7566 also offers a voltage margining capability that shifts the output voltage 5% for validation of system card performance and reliability durin g manufacturing tests. a junc tion temperature indicator conveniently monitors the silicon die temperature, saving time in thermal characterization. an easy-to-use simulation tool is available for download and can be used to modify design parameters such as switching frequency, voltage ripple, ambie nt temperature , as well as view schematics waveforms , efficiency graphs, and complete bom with gerber layout. features ? integrated mosfets ? 6a continuous output current ? up to 96% efficiency ? multiple supply start-up tracking ? built-in 5% voltage margining ? 3v to 6v input voltage ? 0.72 in 2 footprint with compo nents on one side of pcb ? adjustable switching frequency to 1mhz ? oscillator synchronization possible ? 100% duty ratio ? junction temperature indicator ? over-temperature protection ? internal soft-start ? variable output voltage down to 0.8v ? power-good indicator ? 28 ld htssop package ? pb-free plus anneal available (rohs compliant) applications ? point-of-regulation power supplies ? fpga core and i/o supplies ? dsp, cpu core, and io supplies ? logic/bus supplies ? portable equipment related documentation ? technical brief 415 - us ing the el7566 demo board ? easy-to-use applications software simulation tool available at www.intersil.com/dc-dc
el7566 fn7102 rev 7.00 page 2 of 14 may 8, 2006 typical application diagram ordering information part number part marking tape & reel temp range (c) package pkg. dw g. # el7566dre 7566dre - 0 to 85 28 ld htssop mdp0048 el7566dre-t7 7566dre 7 0 to 85 28 ld htssop mdp0048 EL7566DRE-T13 7566dre 13 0 to 85 28 ld htssop mdp0048 el7566drez (note) 7566drez - 0 to 85 28 ld htssop (pb-free) mdp0048 el7566drez-t7 (note) 7566drez 7 0 to 85 28 ld htssop (pb-free) mdp0 048 el7566drez-t13 (note) 7566drez 13 0 to 85 28 ld htssop (pb-free) md p0048 el7566airez (note) 7566airez -40 to 85 28 ld htssop (pb-free) mdp00 48 el7566airez-t7 (note) 7566airez 7 -40 to 85 28 ld htssop (pb-free) mdp0048 el7566airez-t13 (note) 7566airez 13 -40 to 85 28 ld htssop (pb-fre e) mdp0048 note: intersil pb-free plus anneal products employ special pb-fr ee material sets; molding compounds/die attach materials and 10 0% matte tin plate termination finish, which are rohs compliant and compatible wit h both snpb and pb-free solderi ng operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exc eed the pb-free requirements of ipc/jedec j std-020. 8200pf 0.047f 2.7h 150f v out (2.5v, 6a) 100f v in (3v to 6v) 0.22f 270pf comp vref fb vo vtj tm sel lx lx lx lx lx lx nc sgnd cosc stn stp en pg vdd vin vin vin pgnd pgnd pgnd nc 1 2 3 4 28 27 26 25 5 6 7 24 23 22 8 21 9 10 20 19 11 12 13 18 17 16 14 15 r 2 r 1 10k 10k 21.5k c c r c
el7566 fn7102 rev 7.00 page 3 of 14 may 8, 2006 important note: all parameters having min/max specifications are guaranteed. typ values are for information purposes only. unles s otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a absolute maximum ratings (t a = 25c) v in , v dd to sgnd. . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3v to +6.5v vx to pgnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to v in +0.3v sgnd to pgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +0.3v comp, v ref , fb, v o , v tj , tm, sel, pg, en, stp, stn, c osc to sgnd . . . . . -0.3v to v dd +0.3v storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125c operating ambient temperature dre . . . . . . . . . . . . . 0c to +85c operating ambient temperatute aire . . . . . . . . . . .-40c t o +85c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. dc electrical specifications v dd = v in = 3.3v, t a = t j = 25c, c osc = 390pf, unless otherwise specified parameter description conditions min typ max unit v in input voltage range 3 6 v v ref reference accuracy 1.24 1.26 1.28 v v reftc reference temperature coefficient 50 ppm/c v refload reference load regulation 0 < i ref < 50a -1 % v ramp oscillator ramp amplitude 1.15 v i osc_chg oscillator charge current 0.1v < v osc < 1.25v 200 a i osc_dis oscillator discharge current 0.1v < v osc < 1.25v 8 ma i vdd v dd supply current v en = 1 (l disconnected) 2 2.7 5 ma i vdd_off v dd standby current en = 0 1 1.5 ma v dd_off v dd for shutdown 2.4 2.65 v v dd_on v dd for startup 2.6 2.95 v t ot over-temperature threshold 135 c t hys over-temperature hysteresis 20 c i leak internal fet leakage current en = 0, l x = 6v (low fet), l x = 0v (high fet) 10 a i lmax peak current limit 7.8 a r dson1 pmos on resistance 29 50 m ? r dsontc2 nmos on resistance 25 m ? r dsontc r dson tempco 0.2 m ? /c i stp stp pin input pull-down current v stp = v in /2 -4 2.5 a i stn stn pin input pull-up current v stn = v in /2 2.5 4 a v pgp positive power good threshold wit h respect to target output volt age 6 14 % v pgn negative power good threshold with respect to target output volt age -14 -6 % v pg_hi power good drive high i pg = 1ma 2.6 v v pg_lo power good drive low i pg = -1ma 0.5 v v ovp output overvoltage protection 10 % v fb output initial accuracy i load = 0a 0.79 0.8 0.81 v v fb_line output line regulation v in = 3.3v, ? v in = 10%, i load = 0a 0.2 0.5 % gm ea error amplifier transconductance v cc = 0.65v 85 125 165 s v fb_tc output temperature stability 0c < t a < 85c, i load = 3a 1 % f s switching frequency 300 370 440 khz i fb feedback input pull-up current v fb = 0v 100 200 na
el7566 fn7102 rev 7.00 page 4 of 14 may 8, 2006 v en_hi en input high threshold 2.6 v v en_lo en input low threshold 1v i en enable pull-up current v en = 0 -4 -2.5 a tm, s el_hi input high level 2.6 v tm, s el_lo input low level 1v dc electrical specifications v dd = v in = 3.3v, t a = t j = 25c, c osc = 390pf, unless otherwise specified (continued) parameter description conditions min typ max unit pin descriptions pin number pin name pin function 1 comp error amplifier output; pla ce loop compensation components here 2 vref bandgap reference bypass c apacitor; typically 0.022f to 0 .047f to sgnd 3 fb voltage feedback input; connected to external resistor divid er between v out and sgnd for adjustable output; also used for speed-up capacitor connection 4 vo output sense for fixed output option. this pin can be open f or el7566 5 vtj junction temperature monitor output 6 tm stress test enable; allows 5% output movement; connect to s gnd if function is not used 7 sel positive or negative stress select; see text 8, 9, 10, 11, 12, 13 lx inductor drive pin; high current output w hose average voltage equals the regulator output voltage 14, 15 nc not used 16, 17, 18 pgnd ground return of the regulator; connected to the source of the low-side synchronous nmos power fet 19, 20, 21 vin power supply input of the regulator; connected to the drain of the high-side pmos power fet 22 vdd control circuit posit ive supply; connected to v in through an internal 20 ? resistor 23 pg power-good window comparator output; logic 1 when regulator output is within 10% of target output voltage 24 en chip enable, active high; a 2 .5a internal pull-up current enables the device if the pin is left open; a capacitor can be added at this pin to delay the start of a conv erter 25 stp auxilliary supply tracki ng positive input; tied to regulat or output to synchronize start-up with a second supply; leave open for standalone operation; 2a internal pull- up current 26 stn auxiliary supply tracking negative input; connect to outpu t of a second supply to synchronize start-up; leave open for standalone operation; 2a internal pull-up curre nt 27 cosc oscillator timing capaci tor (see performance curves) 28 sgnd control circuit negative supply or signal ground
el7566 fn7102 rev 7.00 page 5 of 14 may 8, 2006 block diagram drivers pwm controller power tracking current sense voltage reference oscillator 2.2nf stp stn sgnd power power fet fet 390pf 0.047f 2.7h v out (2.5v, 6a) 150f v ref c osc pgnd v tj fb en - + pg v ref v in v in v dd 100f v o r 1 v dd tm sel 20 ? ea comp 0.22f v dd r 2 r c c c junction temperature
el7566 fn7102 rev 7.00 page 6 of 14 may 8, 2006 typical performance curves v in = v d = 5v, v o = 2.5v, i o = 6a, f s = 500khz, l = 2.7h, c in = 100f, c out = 150f, t a = 25c unless otherwise noted. figure 1. efficiency (v in = 5v) figure 2. efficiency (v in = 3.3v) figure 3. v ref vs temperature figure 4. v tj vs temperature figure 5. v en_hi & v en_low vs v dd figure 6. f s vs c osc 100 95 90 85 80 75 70 65 60 012 456 3 efficiency (%) i o (a) v o =3.3v v o =0.8v v o =2.5v v o =1.8v v o =1v v o =1.2v 100 95 90 85 80 75 70 65 60 012 456 3 efficiency (%) i o (a) v o =0.8v v o =2.5v v o =1.2v v o =1v v o =1.8v 1.265 1.255 1.25 1.24 1.245 050100150 v ref junction temperature (c) 1.26 v dd =3.3v v dd =5v 1.6 1.4 1.1 1 0 050100150 v tj junction temperature (c) 1.5 v dd =3.3v v dd =5v 1.2 1.3 4 2 1.5 1 3456 v dd (v) 3.5 v en_hi v en_low 2.5 3 3.5 4.5 5.5 1200 500 200 0 100 300 500 700 f s (khz) c osc (pf) 1000 v dd =3.3v v dd =5v 600 800 200 400 600
el7566 fn7102 rev 7.00 page 7 of 14 may 8, 2006 figure 7. f s vs load current figure 8. load regulations figure 9. htssop thermal resistance vs pcb area (no air flow) figure 10. package power dissipation vs ambient temperature figure 11. package power dissipation vs ambient temperature typical performance curves v in = v d = 5v, v o = 2.5v, i o = 6a, f s = 500khz, l = 2.7h, c in = 100f, c out = 150f, t a = 25c unless otherwise noted. (continued) 526 508 506 504 0246 switching frequency i o (a) 520 v in =3.3v v in =5v 512 516 135 524 518 510 514 522 0.1 -0.25 -0.3 -0.35 0246 (%) i o (a) 0 -0.15 135 -0.05 -0.2 -0.1 0.05 50 45 40 35 30 25 123456789 pcb area (in 2 ) ? ja (c/w) condition: 28-pin htssop thermal pad soldered to 2-layer pcb with 0.039" thickness and 1 oz. copper on both sides jedec jesd51-7 high e ffective thermal conductivity test board 3.5 2.5 2.0 1.0 0.5 0 0 25 50 75 100 150 ambient temperature (c) allowable power dissipation (w) 125 85 1.5 ? j a = 3 0 c / w h t s s o p 2 8 3.0 1.00 0.90 0.30 0 0 255075100 150 ambient temperature (c) allowable power dissipation (w) 85 ? j a = 1 1 0 c / w h t s s o p 2 8 0.70 0.20 0.50 125 jedec jesd51-3 low effective thermal conductivity test board 0.10 0.40 0.60 0.80
el7566 fn7102 rev 7.00 page 8 of 14 may 8, 2006 waveforms v in = v d = 5v, v o = 2.5v, i o = 6a, f s = 500khz, l = 2.7h, c in = 100f, c out = 150f, t a = 25c unless otherwise noted. figure 12. start-up figure 13. steady-state operation figure 14. shut-down fig ure 15. transient response figure 16. voltage margining fig ure 17. overvoltage shut-down v in (5v/div) i in (2a/div) v o (2v/div) pg 0.5ms/div ? v in (200mv/div) i l (2a/div) v lx (5v/div) ? v o (50mv/div) 1s/div v en i in (2a/div) v o (2v/div) 50s/div 4.5a i o ? v o (100mv/div) 1.5a 100s/div tm sel ? v o (200mv/div) 1ms/div pg v o (2v/div) v lx (5v/div) 0.5ms/div
el7566 fn7102 rev 7.00 page 9 of 14 may 8, 2006 detailed description the el7566 is a 6a capable bu ck regulator operating from an input voltage range of 3v to 6v. the duty cycle can be adjusted from 0% to 100% allo wing for a wide range of programmable output voltages. patented on-chip resistorless current-sensing enables current mode control for excellent step load respons e. overcurrent, overvoltage, input undervoltage, and therma l protection is integrated along with soft-start and pow er-up sequencing features to produce an overall robust power solution for general purpose applications. el7566dre vs. el7566aire the el7566aire includes the following feature changes from the el7566dre: ? up to 6a current sinking capability ? expanded temperature range: -40 o c to 85 o c ? no overvoltage protection start-up the el7566 employs a digital soft-start feature to suppress the in-rush current needed to charge the output capacitance and smoothly ramp the output voltage to regulation (see figure 12). the normal start-up process begins when the input voltage reaches the ri sing por threshold (~2.8v) and en pin is transitioned high b y an internal 2.5a current source. the output voltage is then digitally ramped to regulation over a 2ms period. the 2ms soft start-up time can be extended if needed by configuring the stp and stn pins. (refer to full start-up control section). if the input voltage is ramped slowly, soft-start may be initiated before the input supply has reached regulation. the lower input voltage will have increased current demand during start-up and may risk an overcurrent event. to prevent such an event from occurring, a capacitor can be placed from the en pin to gnd to program a delay between when the rising por threshold for vin is met and when soft- start begins. the programmable delay time, t d , is governed by equation 1. where: ?c en is the capacitance at en pin ?v en_hi is the en input high level (function of v dd voltage, see figure 5) ?i en is the en pin pull-up current, nominal 2.5a steady-state operation under all steady-state conditi ons the converter will operate in fixed frequency continuous-conducti on mode. for fast transient response and ease of controllability, a peak current-mode control method is employed. the inductor current is sensed from the u pper pmos. this current signal serves as the ramp to the pwm comparator and is compared against the difference signal generated by the transconductance error amplif ier. slope compensation for the ramp is used to allow for 100% duty cycle operation (see figure 20). the pulse-width m odulated square wave output of the pwm comparator is ampli fied and serves as the gate drive signals for the switching power fets. 100% duty ratio el7566 uses cmos as inter nal synchronous power switches. the upper and low er switches are pmos and nmos respectively. the upper pmos saves the need for a boot capacitor normally seen in nmos/nmos half-bridges. figure 18. adjustable start-up figure 19. tracking start-up waveforms v in = v d = 5v, v o = 2.5v, i o = 6a, f s = 500khz, l = 2.7h, c in = 100f, c out = 150f, t a = 25c unless otherwise noted. (continued) v in (5v/div) i in (2a/div) v o (2v/div) pg 5ms/div v in (5v/div) v o1 =2.5v v o2 =1.8v 5ms/div t d c en v en_hi i en -------------------- ? =
el7566 fn7102 rev 7.00 page 10 of 14 may 8, 2006 it also allows 100% tu rn-on of the upper pmos switch, achieving v o close to v in . the maximum achievable v o is: where r l is the dc resistance on the inductor and r dson1 is the pmos on-resist ance, nominally 30m ? at room temperature with a temperature coefficient of 0.2m ? /c. output voltage selection the output voltage can be as high as the input voltage minus the pmos and inductor voltage drops (as seen previously in equation 2). referring to the typical application circuit on page 2, use r 1 and r 2 to set the output voltage according to the following formula: some standard values of r 1 and r 2 are listed in table 1. it is important that the series combination of r1 and r2 is large enough as to not draw excessive current from the output. voltage margining the el7566 has built-in 5% l oad stress test (commonly called voltage margining) function. combinations of tm and sel set the margins shown in t able 2. when this function is not used, both pins should be connected to sgnd, either directly or through a 10k ? resister. figure 16 shows this feature. switching frequency the regulator has a programma ble switching frequency of 200khz to 1mhz. the switching frequency is generated by a relaxation comparator and adjus ted by a capacitor from the osc pin to gnd (c osc ). the triangle waveform has 95% duty ratio and runs from 0.2v t o 1.2v. refer to the curve in figure 6 for the app ropriate value of c osc for the desired frequency. if external synchroni zation is desired, the circuit in figure 21 can be used. always choose the converter self-switching frequency 20% lower than the sync frequen cy to accommodate component variations. protection features the el7566 features a wide range of protective measures to prevent the persistence of damaging system conditions. these features are overvoltage, overcurrent, power-on- reset (por), and thermal shutdown protection. overvoltage protection (ovp) the el7566 monitors the outp ut voltage and will shut down if it exceeds 110% of the set r egulation point. this is accomplished by comparing the reference to the fb pin voltage. if an overvoltage condi tion is met, the controller wil l turn the high-side switch off, the low-side switch on, and pull pgood low. the converter will not latch off and will proceed with a soft-start as soon as the fault condition is cleared. overcurrent protection (ocp) the current information for pwm ramp generation is also used for overcurrent protecti on. the measured current is compared against a preset overcurrent threshold (~7-10a). if the output current exceeds t he threshold, the output will shut down by turning off the high-side switch and turning the low-side switch on. this even t, like ovp, will not latch the converter off. a soft-start will be initiated when the fault is cleared. power-on reset (por) to ensure proper regulator o peration, a power-on reset feature monitors the input v oltage. when adequate input voltage is achieved (v dd > 2.8v), the converter is allowed to soft-start. however, if v dd falls below 2.5v, the regulator will shut down in the same manner as ovp or ocp. thermal protection and junction temperature indicator an internal temperature sensor continuously monitors the junction temperature. if the junction temperature exceeds 135c, the regulator is in a fault conditi on and will shut down. when the temperature falls back below 110c, the regulator goes through the so ft-start procedure again. table 1. v o (v) r 1 (k ? )r 2 (k ? ) 0.8 2 open 12.4910 1.2 4.99 10 1.5 10 11.5 1.8 12.7 10.2 2.5 21.5 10 3.3 36 11.5 table 2. condition tm sel v o normal 0 x nominal high margin 1 1 nominal + 5% low margin 1 0 nominal - 5% v o v in r l r dson1 + ?? i o ? C = v o 0.8 1 r 1 r 2 ------ - + ?? ?? ?? ? = el7566 c osc 100pf external sync source figure 20. external sync circuit
el7566 fn7102 rev 7.00 page 11 of 14 may 8, 2006 the v tj pin reports a voltage proportional to the junction temperature. equation 3 illustrates the relationship and can be used to accurately evalu ate thermal design points. full start-up control the el7566 offers full start-u p control. the core of this control is a start-up comparat or in front of the main pwm controller. the stp and stn are the inputs to the comparator, whose hi output forces the pwm comparator to skip switching cycles. the user can choose any of the following control configurations: adjustable soft-start in this configuration, the ramp -up time is adjustable to any time longer than the building soft-start time of 2ms. the approximate ramp-up time, t st , is: cascade start-up in this configuration, en pin of regulator 2 is connected to the pg pin of regula tor 1 (figure 22). v o2 will only start after v o1 is good. linear start-up in the linear start-up tracking co nfiguration, the regulator wi th lower output voltage, v o2 , tracks the one with higher output voltage, v o1 . offset start-up compared with the cascade star t-up, this configuration allows regulator 2 to begin the start-up process when v o1 reaches a particular value of v ref *(1+r b /r a ) before pg goes hi, where v ref is the regulator reference voltage. v ref =1.26. component selection input capacitor the main functions of the input capacitor(s) are to maintain the input voltage steady and t o filter out the pulse current passing through the upper swit ch. the root-mean-square value of this current is: for a wide range of v in and v o . for long-term reliability, the i nput capacitor or combination o f capacitors must have the current rating higher than i in,rms . use x5r or x7r type cerami c capacitors, or spcap or poscap types of polymer capaci tors for their high current handling capability. t j 75 1.2 v tj C 0.00384 ------------------------ + = t st rc v o v in --------- ?? ?? ?? = v in stp v o - + stn 0.1f 200k v o t st r c el7566 figure 21. adjustable start-up el7566 v in el7566 en pg v o2 v o1 v o2 v o1 figure 22. cascade start-up v in stp v o1 - + stn c r - + v in v o2 v o1 v o2 el7566 el7566 figure 23. linear start-up tracking v in v o1 - + v in v o2 v ref r b r a v o1 v o2 v ref (1+r b /r a ) el7566 el7566 figure 24. offset start-up tracking i in,rms v o v in v o C ?? ? v in ----------------------------------------------- i o 1/2 ? ? i ? o ? =
el7566 fn7102 rev 7.00 page 12 of 14 may 8, 2006 inductor the nmos positive current limit is set at about 8a. for optimal operation, t he peak-to-peak inductor current ripple ? i l should be less than 1a. the following equation gives the inductance value: the peak current the inductor sees is: when inductor is chosen, it must be rated to handle the peak current and the average current of i o . output capacitor output voltage ripple and tr ansient response are the predominant factors when choo sing the output capacitor. initially, output capacitance should be sized with an esr to satisfy the output ripple ? v o requirement: when a step load change, ? i o , is applied to the converter, the initial voltage drop can be appro ximated by esr* ? i o . the output voltage will continue to drop until the control loop begins to correct the output v oltage error. increasing the output capacitance will lessen the impact of load steps on output voltage. increasing l oop bandwidth will also reduce output voltage deviation unde r step load conditions. some experimentation with converter ba ndwidth and output filtering will be necessary t o generate a goo d transient response (reference figure 15). as with the input capacitor, it is recommended to use x5r or x7r type of ceramic capaci tors. spcap or poscap type polymer capacitors can also b e used for the low esr and high capacitance requirements of these converters. generally, the ac current rating of the output capacitor is not a concern because the rms current is only 1/8 of ? i l . loop compensation current-mode control in system forces the inductor current to be proportional to the error signal. this has the advantage of eliminating the double pole r esponse of the output filter, and reducing complexity in the overall loop compensation. a simple type 1 compensator is adequate to generate a stable, high-bandwidth converter. the compensation resister is decided by: where: ?gm pwm is the transconductance of the pwm comparator, gm pwm = 120s ? esr is the esr of th e output capacitor ?c out is output capacitance ?gm ea is the transconductance of the error amplifier, gm ea = 120s ?f c is the intended crossover frequency of t he loop. for best performance, set this va lue to about one-tenth of the switching frequency. ? once r c is chosen, c c is decided by: design example a 5v to 2.5v converter wit h a 6a load requirement. 1. choose the input capacitor the input capacitor or combinat ion of capacitors has to be able to take about 1/2 of the output current, e.g., 3a. panasonic eefud0j101xr is rated at 3.3a, 6.3v, meeting the above criteria. 2. choose the inductor. set the converter switching frequency at 500khz: ? i l = 1a yields 2.3h. leave some margin and choose l = 2.7h. coilcraft's do3 316p-272hc has the required current rating. 3. choose the output capacitor l = 2.7h yields about 1a inductor ripple current. if 25mv of ripple is desired, c out 's esr needs to be less than 25m ? . panasonic's eefud0g151xr 150f has an esr of 12m ? and is rated at 4v. esr is not the only factor decid ing the output capacitance. as discussed earlier, output vo ltage droops less with more capacitance when converter i s in load transient. multiple iterations may be needed bef ore final components are chosen. 4. loop compensation 50khz is the intended crosso ver frequency. with the conditions r c and c c are calculated as: r c = 10.5k ? and c c = 8900pf, round to standard value of 8200pf. l v in ? v o ? v o ? C v in ? i l f s ? ? -------------------------------------------- = i lpk i o ? i l 2 -------- + = ? v o ? i l esr ? = r c i o vfb ------------ f c 2 ? esr ? r out ? c out ? + ? ? ? gm pwm gm ea ? --------------------------------------------------------------- ---------------------------------- ? = r out v o i o ------- - = c c 1.5 c out r out r c --------------- - ? ? = l v in ? v o ? v o ? C v in ? i l f s ? ? -------------------------------------------- =
el7566 fn7102 rev 7.00 page 13 of 14 may 8, 2006 for convenience, table 3 lists the compensation values for frequently used output voltages. thermal management the el7566 is packaged in a thermally-efficient htssop-28 package, which utilizes the ex posed thermal pad at the bottom to spread heat through pcb metal. therefore: 1. the thermal pad must b e soldered to the pcb. 2. maximize the pcb area. 3. if a multiple layer pcb is used, thermal vias (13 to 25 mil) must be placed underneath the thermal pad to connect to ground plane(s). do not place thermal reliefs on the vias. figure 25 shows a t ypical connection. the thermal resistance for this package is as low as 26c/w for 2 layer pcb of 0.39" thickness (see figure 9). the actual junction temperature can be measured at v tj pin. the thermal performance of the ic is heavily dependent on the layout of the pcb. the use r should exercise care during the design phase to ensure th e ic will operate within the recommended environmental conditions. layout considerations the layout is very i mportant for the conv erter to function properly. follow these tips for best performance: 1. separate the power ground ( ) and signal ground ( ); connect them only at one p oint right at the sgnd pin 2. place the input capacitor(s) as close to v in and pgnd pins as possible 3. make as small as possible th e loop from lx pins to l to c o to pgnd pins 4. place r 1 and r 2 pins as close to th e fb pin as possible 5. maximize the copper area around the pgnd pins; do not place thermal relief around them 6. thermal pad should be soldered to pcb. place several via holes under the chip to the ground plane to help heat dissipation the demo board is a g ood example of layout based on this outline. please refer to t he el7566 application brief. table 3. compensation values v o (v) r c (k ? )c c (pf) 3.3 13.7 8200 2.5 10.5 8200 1.8 7.68 8200 1.5 6.49 8200 1.2 5.23 8200 1 4.42 8200 0.8 3.57 8200 ground plane connection component side connection figure 25. pcb layout - 28-pin htssop package
fn7102 rev 7.00 page 14 of 14 may 8, 2006 el7566 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas ll c 2004-2006. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. package outline drawing note: the package drawing shown here may not be the latest versi on. to check the latest revision , please refer to the intersil website at http://www.intersil.com/design/packages/index.asp

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